This invention relates to programmable logic array integrated circuit devices, and more particularly to the interconnection resources that are provided in such devices.
Certain programmable logic array devices have regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Examples of this general type of device are shown in Pedersen et al. U.S. Pat. No. 5,260,610, Cliff et al. U.S. Pat. No. 5,260,611, Cliff et al. U.S. Pat. No. 5,689,195, and Cliff et al. U.S. patent application Ser. No. 08/672,676, filed Jun. 28, 1996. (All of these references are hereby incorporated by reference herein.) Generally in such devices, horizontal conductors are associated with each row of logic regions for conveying signals to, from, and between the logic regions in that row. Similarly, vertical conductors are associated with each column of logic regions for conveying signals to, from, and between the logic regions in that column or the rows of logic regions along that column. Programmable (or, in some limited instances, fixed) interconnections are provided for connecting (1) signals on the horizontal conductors associated with each row to inputs of the logic regions in that row, (2) outputs of the logic regions in each row to the horizontal conductors associated with that row, and (3) the horizontal conductors associated with each row to the vertical conductors crossing that row. Additional programmable (or, in some limited instances, fixed) connections may be provided for connecting the outputs of the logic regions in each column to the vertical conductors associated with that column.
Exclusive association of each row of logic regions with its own group of horizontal conductors, and similar exclusive association of each column of logic regions with its own group of vertical conductors, may increase the overall numbers of such conductors that are needed on a device or may limit usability of the device for given numbers of such conductors. For example, if the logic regions in each row can only use the horizontal conductors associated with that row, each row must be provided with enough horizontal conductors to satisfy the maximum possible demand for horizontal interconnection along a row. (It will be understood that the "maximum possible demand" referred to may not be an absolute maximum, but only a somewhat smaller demand, which the device designer has concluded is sufficient to meet the requirements of most of the probable uses of the device.) This may mean that substantial numbers of horizontal conductors are unused in rows that do not require as much horizontal interconnection. As another example, because all interconnections between rows--even immediately adjacent rows--require use of vertical conductors, the demand for vertical conductors is increased by the unique or exclusive association of each row with a particular group of horizontal conductors.
In view of the foregoing, it is an object of this invention to improve the interconnection resources that are provided on programmable logic array integrated circuit devices.
It is a more particular object of this invention to provide programmable logic array devices that make more efficient use of the interconnection conductors with which they are provided.
It is still another object of the invention to allow programmable logic devices to be provided with fewer interconnection conductors with no reduction in the usability of the devices, or to increase the usability of the devices for a given amount of interconnection conductor resources.